In deep sub-micron integrated circuit technology, an embedded static random access memory (SRAM) device has become a popular storage unit of high speed communication, image processing and system-on-chip (SOC) products. For example, a dual port (DP) SRAM device allows parallel operation, such as 1R (read) 1W (write), or 2R (read) in one cycle, and therefore has higher bandwidth than a single port SRAM. In advanced technologies with decreased feature size and increased packing density, low loading and high speed of the cell structure are important factors in embedded memory and SOC products. Various gate structures are implemented to achieve high packing density and high speed. For example, a U-shaped gate structure is employed in the SRAM structure. However, the U-shaped gate structure induces potential issues including pull-down (PD) device variation and integration concerns on fin-like field-effect transistor (FinFET) structure. Furthermore, the critical dimension uniformity (CDU) in the U-shaped gate structure also introduces necking and leakage problems. Accordingly, the U-shaped gate structure impacted the SRAM cell stability and limited the scaling (or shrink) capability. It is therefore desired to have a new structure and method to address the above issues.